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june 2009 ? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 mm74hc595 ? 8-bit shift register with output latches mm74hc595 8-bit shift register with output latches features ? low quiescent current: 80a maximum (74hc series) ? low input current: 1a maximum ? 8-bit serial-in, parallel-out shift register with storage ? wide operating voltage range: 2v?6v ? cascadable ? shift register has direct clear ? guaranteed shift frequency: dc to 30mhz description the mm74hc595 high-speed shift register utilizes advanced silicon-gate cmos technology. this device possesses the high noise immunity and low power consumption of standard cmos integrated circuits, as well as the ability to drive 15 ls-ttl loads. this device contains an eight-bit serial-in, parallel-out, shift register that feeds an eight-bit d-type storage register. the storage register has eight 3-state outputs. separate clocks are provided fo r both the shift register and the storage register. the sh ift register has a direct- overriding clear, serial input, and serial output (standard) pins for cascading. both the shift register and storage register use posit ive-edge triggered clocks. if both clocks are connected t ogether, the shift register state is one clock pulse ahead of the storage register. the 74hc logic family is speed, function, and pin-out compatible with the standard 74ls logic family. all inputs are protected from damage due to static discharge by internal diode clamps to v cc and ground. ordering information part number operating temperature range eco status package packing method mm74hc595m -40 to +85c rohs tubes mm74hc595mx -40 to +85c rohs 16-lead, small outline integrated circuit (soic), jedec ms-012, 0.150 inch narrow tape and reel mm74hc595sj -40 to +85c rohs tubes MM74HC595SJX -40 to +85c rohs 16-lead, small outline package (sop), eiaj type ii, 5.3mm wide tape and reel mm74hc595mtc -40 to +85c rohs tubes mm74hc595mtcx -40 to +85c rohs 16-lead, thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide tape and reel mm74hc595n -40 to +85c rohs 16-lead, plastic dual in-line package (pdip), jedec ms-001, 0.300 inch wide tubes for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 2 mm74hc595 ? 8-bit shift register with output latches block diagram figure 1. logic diagram (positive logic)
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 3 mm74hc595 ? 8-bit shift register with output latches pin configuration figure 2. pin configuration pin definitions pin # name description 1 q b output bit b 2 q c output bit c 3 q d output bit d 4 q e output bit e 5 q f output bit f 6 q g output bit g 7 q h output bit h 8 gnd ground 9 q? h serial data output 10 sclr shift register clear 11 sck shift register clock input 12 rck storage register clock input 13 g output enable 14 ser serial data input 15 qa output bit a 16 v cc supply voltage truth table rck sck sclr g function x x x h qa through q h = 3-state x x l l shift register clocked; q? h = 0 x h l shift register clocked; q n = q n-1 , q 0 = ser x h l contents of shift; register transferred to output latches l = logic level low h = logic level high x = don?t care = transition from low to high level
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 4 mm74hc595 ? 8-bit shift register with output latches absolute maximum ratings (1) stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 7.0 v v in dc input voltage -1.5 to v cc+ 1.5 v v out dc output voltage -0.5 to v cc+ 0.5 v i ik , i ok clamp diode current 20 ma i out dc output current, per pin 35 ma i cc dc vcc or gnd current, per pin 70 ma t stg storage temperature range -65 +150 c pdip (2) 600 p d power dissipation soic package only 500 mw t l lead temperature +260 c esd electrostatic discharge capability human body model, jesd22-a114 4000 v notes: 1. unless otherwise specified all voltages are referenced to ground. 2. power dissipation temperature derating, plasti c package (pdip);12mw/c from -65 to +85c. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage 2 6 v v in , v out dc input or output voltage 0 v cc v t a operating temperature range -40 +85 c v cc =2.0v 1000 v cc =4.5v 500 t r ,t f input rise and fall times v cc =6.0v 400 ns
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 5 mm74hc595 ? 8-bit shift register with output latches electrical characteristics (3) t a =25c t a =-40 to 85c t a =-55 to 125c symbol parameter conditions v cc typ. guaranteed limits units 2.0v 1.50 1.50 1.50 4.5v 3.15 3.15 3.15 v ih minimum high level input voltage 6.0v 4.20 4.20 4.20 v 2.0v 0.50 0.50 0.50 4.5v 1.35 1.35 1.35 v il minimum low level input voltage 6.0v 1.80 1.80 1.80 v 2.0v 2.00 1.90 1.90 1.90 4.5v 4.50 4.40 4.40 4.40 minimum high level output voltage v in =v ih or v il ? i out ? 20a 6.0v 6.00 5.90 5.90 5.90 v ? i out ? 4.0ma 4.5v 4.20 3.98 3.84 3.70 q? h v in =v ih or v il ? i out ? 5.2ma 6.0v 5.20 5.48 5.34 5.20 v ? i out ? 6.0ma 4.5v 4.20 3.98 3.84 3.70 v oh q a through q h v in =v ih or v il ? i out ? 7.8ma 6.0v 5.70 5.48 5.34 5.20 v 2.0v 0 0.10 0.10 0.10 4.5v 0 0.10 0.10 0.10 minimum low level output voltage v in =v ih or v il ? i out ? 20a 6.0v 0 0.10 0.10 0.10 v ? i out ? 4.0ma 4.5v 0.20 0.26 0.33 0.40 q? h v in =v ih or v il ? i out ? 5.2ma 6.0v 0.20 0.26 0.33 0.40 v ? i out ? 6.0ma 4.5v 0.20 0.26 0.33 0.40 v ol q a through q h v in =v ih or v il ? i out ? 7.8ma 6.0v 0.20 0.26 0.33 0.40 v i in maximum input output leakage v in =v cc or gnd 6.0v 0.1 1.0 1.0 a i oz maximum 3- state output leakage v out =v cc or gnd g=v ih 6.0v 0.5 5.0 10 a i cc maximum quiescent supply current v in =v cc or gnd i out =a 6.0v 8.0 80 160 a note: 3. for a power supply of 5v 10%, the worst-case output voltages (v oh , and v ol ) occur for hc at 4.5v. the 4.5v values should be used when designing with this supply. worst-case v ih and v il occur at v cc = 5.5v and 4.5v, respectively; v ih value at 5.5v is 3.85v. the worst-case leakage current (i in , i cc , and i oz ) occurs for cmos at the higher voltage; so the 6.0v values should be used.
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 6 mm74hc595 ? 8-bit shift register with output latches ac electrical characteristics v cc = 5v, t a = 25 c, t r = t f = 6ns. symbol parameter conditions ty p. guaranteed limit units f max maximum operating frequency of sck 50 30 mhz maximum propagation delay, sck to q? h 12 20 t phl ,t plh maximum propagation delay, rck to q a thru q? h c l =45pf 18 30 ns t pzh ,t pzl maximum output enable time from g to q a thru q? h r l =1k , c l =45pf 17 28 ns t phz ,t plz maximum output disable time from g to q a thru q? h r l =1k , c l =45pf 15 25 ns minimum setup time from ser to sck 20 ns minimum setup time from sclr to sck 20 ns t s minimum setup time from ser to rck (4) 40 ns t h minimum hold time from ser to sck 0 ns t w minimum pulse width of sck or rck 16 ns note: 4. this setup time ensures the register will see stabl e data from the shift-register outputs. the clocks may be connected together in which case the storage register state will be one clock pulse behind the shift register.
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 7 mm74hc595 ? 8-bit shift register with output latches electrical characteristics v cc = 2.0 ? 6.0v, c l = 50pf, t r = t f =6ns unless otherwise specified. t a =25c t a =-40 to 85c t a =-55 to 125c symbol parameter conditions v cc typ. guaranteed limits units 2.0v 10.0 6.0 4.8 4.0 4.5v 45.0 30.0 24.0 20.0 f max maximum operating frequency c l =50pf 6.0v 50.0 35.0 28.0 24.0 ns c l =50pf 2.0v 58.0 210.0 235.0 315.0 c l =150pf 2.0v 83.0 294.0 367.0 441.0 c l =50pf 4.5v 14.0 42.0 53.0 63.0 c l =150pf 4.5v 17.0 58.0 74.0 88.0 c l =50pf 6.0v 10.0 36.0 45.0 54.0 maximum propagation delay, sck to q? h c l =150pf 6.0v 14.0 50.0 63.0 76.0 ns c l =50pf 2.0v 70.0 175.0 220.0 265.0 c l =150pf 2.0v 105.0 245.0 306.0 368.0 c l =50pf 4.5v 21.0 35.0 44.0 53.0 c l =150pf 4.5v 28.0 49.0 61.0 74.0 c l =50pf 6.0v 18.0 30.0 37.0 45.0 maximum propagation delay, rck to q a thru q? h c l =150pf 6.0v 26.0 42.0 53.0 63.0 ns 2.0v 175.0 221.0 261.0 4.5v 35.0 44.0 52.0 t phl ,t plh maximum propagation delay, sclr to q? h 6.0v 30.0 37.0 44.0 ns c l =50pf 2.0v 75.0 175.0 220.0 265.0 r l =1k c l =150pf 2.0v 100.0 245.0 306.0 368.0 c l =50pf 4.5v 15.0 35.0 44.0 53.0 c l =150pf 4.5v 20.0 49.0 61.0 74.0 c l =50pf 6.0v 13.0 30.0 37.0 45.0 t pzh ,t pzl maximum output enable time from g to q a thru q? h c l =150pf 6.0v 17.0 42.0 53.0 63.0 ns 2.0v 75.0 175.0 220.0 265.0 4.5v 15.0 35.0 44.0 53.0 t phz ,t plz maximum output disable time from g to q a thru q? h r l =1k , c l =50pf 6.0v 13.0 30.0 37.0 45.0 ns continued on the following page?
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 8 mm74hc595 ? 8-bit shift register with output latches electrical characteristics v cc = 2.0 ? 6.0v, c l = 50pf, t r = t f =6ns unless otherwise specified. t a =25c t a =-40 to 85c t a =-55 to 125c symbol parameter conditions v cc typ. guaranteed limits units 2.0v 100 125 150 4.5v 20 25 30 t s minimum setup time from ser to sck r l =1k , c l =50pf 6.0v 17 21 25 ns 2.0v 50 63 75 4.5v 10 13 15 t r minimum removal time from sclr to sck 6.0v 9 11 13 ns 2.0v 100 125 150 4.5v 20 25 30 t s minimum setup time from sck to rck 6.0v 17 21 26 ns 2.0v 5 5 5 4.5v 5 5 5 t h minimum hold time from ser to sck 6.0v 5 5 5 ns 2.0v 30 80 100 120 4.5v 9 16 20 24 t w minimum pulse width of sck or sclr 6.0v 8 14 18 22 ns 2.0v 1000 1000 1000 4.5v 500 500 500 t r ,t f maximum input rise and fall time, clock 6.0v 400 400 400 ns 2.0v 25 60 75 90 4.5v 7 12 15 18 maximum output rise and fall time q a -q h 6.0v 6 10 13 15 ns 2.0v 75 95 110 4.5v 15 19 22 t thl ,t tlh maximum output rise and fall time q? h 6.0v 13 16 19 ns g=v cc 90 c pd power dissipation capacitance, outputs enabled (5) g=gnd 150 pf c in maximum input capacitance 5 10 10 10 pf c out maximum output capacitance 15 20 20 20 pf note: 5. c pd determines the no load dynamic power consumption, p d = c pd v cc 2 f + i cc v cc , and the no load dynamic current consumption, i s = c pd v cc f + i cc .
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 9 mm74hc595 ? 8-bit shift register with output latches timing diagram figure 3. timing diagram note: 6. implies that the output is in 3-state mode. xxx
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 10 mm74hc595 ? 8-bit shift register with output latches physical dimensions x 45 detail a scale: 2:1 8 0 notes: unless otherwise specified a) this package conforms to jedec ms-012, variation ac, issue c. b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash and tie bar protrusions d) conforms to asme y14.5m-1994 e) landpattern standard: soic127p600x175-16am f) drawing file name: m16arev12. seating plane gage plane c c 0.10 see detail a land pattern recommendation pin one indicator 1 16 8 m 0.25 9 cba b a 5.6 1.27 0.65 1.75 10.00 9.80 8.89 6.00 1.27 (0.30) 0.51 0.35 1.75 max 1.50 1.25 0.25 0.10 0.25 0.19 (1.04) 0.90 0.50 0.36 (r0.10) (r0.10) 0.50 0.25 4.00 3.80 figure 4. 16-lead, small outline integrated circuit (soic), jedec ms-012, 0.150 inch narrow package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 11 mm74hc595 ? 8-bit shift register with output latches physical dimensions figure 5. 16-lead, small outline package (sop), eiaj type ii, 5.3mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 12 mm74hc595 ? 8-bit shift register with output latches physical dimensions 0.65 4.40.1 mtc16rev4 0.11 4.55 5.00 5.000.10 12 7.35 4.45 1.45 5.90 figure 6. 16-lead, thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 13 mm74hc595 ? 8-bit shift register with output latches physical dimensions 16 9 8 1 notes: unless otherwise specified a this package conforms to jedec ms-001 variation bb b) all dimensions are in millimeters. d) conforms to asme y14.5m-1994 e) drawing file name: n16erev1 19.68 18.66 6.60 6.09 c) dimensions are exclusive of burrs, mold flash, and tie bar protrusions 3.42 3.17 3.81 2.92 (0.40) 2.54 17.78 0.58 0.35 1.78 1.14 5.33 max 0.38 min 8.13 7.62 0.35 0.20 15 0 8.69 a a top view side view figure 7. 16-lead, plastic dual in-line p ackage (pdip), jedec ms-001, 0.300 inch wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 1983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc595 ? rev. 1.0.2 14 mm74hc595 ? 8-bit shift register with output latches

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